CV

Basics

Name Youngjin (Luke) Kim
Label PhD Student
Email ykim9554@usc.edu

Work

  • 2026.05 - 2026.08
    PhD Intern, Machine Learning Architecture Systems
    Keysight Technologies
    Supervisor: Dr. Fabio Alessio Marino, Calabasas, CA (Incoming)
    • Developing autonomous neural architecture generation and meta-learning frameworks in C++/CUDA and libtorch, targeting operator-learning model families (GNNs, GNOs, FNOs, and Transformer variants) for signal integrity applications
    • Prototyping architecture controllers that adapt model topology, receptive fields, and operator depth based on real-time learning feedback for resolution-invariant signal integrity ML architectures
  • 2025.01 - Present
    Graduate Research Assistant
    University of Southern California (USC)
    Research on EDA for 2.5D/3D IC design and machine learning for EDA under Professor Sungkyu Lim
    • EDA for 2.5D/3D IC Design
    • Machine Learning for EDA
  • 2024.05 - 2024.08
    Intern, Controller Development
    Samsung Memory Division
    Signal Processing Task Group, Algorithm Part - AI Storage Solution for Near-Data Processing
    • Designed and implemented hardware-accelerated vector search engine for AI storage, achieving 20× speedup over CPU baseline
    • Developed high-performance IVF+PQ algorithm pipeline on FPGA using C/C++-based HLS, optimizing memory access patterns and computational throughput
    • Architected prefetching mechanisms for metadata filtering, focusing on data pipeline efficiency and latency reduction
  • - Present
    Undergraduate Researcher
    High-Speed Circuits Lab, Yonsei University
    • Developed FPGA-based digital control algorithms for Silicon Micro Ring Modulators with real-time adaptive feedback
    • Built Python-based simulation framework for thermal crosstalk modeling and compensation in photonic systems
    • Implemented iterative optimization algorithms for multi-channel thermal interaction prediction
  • - Present
    Undergraduate Researcher
    HAI Lab, Yonsei University
    • Designed custom RISC-V processor architecture with reconfigurable computing array for matrix multiplication acceleration, including custom ISA extensions and assembly-level optimization
    • Implemented hardware description in Chisel, focusing on architecture topology optimization and computational efficiency for ML workloads (OpenGeMM)

Education

  • 2025.01 - 2030.01

    Los Angeles, CA

    Ph.D.
    University of Southern California (USC)
    Electrical and Computer Engineering
    • 2.5D/3D IC Design
    • Power Delivery Networks
    • Machine Learning for EDA
  • 2019.03 - 2025.02

    Seoul, South Korea

    Bachelor of Science
    Yonsei University
    Electrical and Electronic Engineering

Awards

Publications